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NXP Semiconductors /MIMXRT1011 /GPC /CNTR

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Interpret as CNTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MEGA_PDN_REQ_0)MEGA_PDN_REQ 0 (MEGA_PUP_REQ_0)MEGA_PUP_REQ 0 (PDRAM0_PGE_0)PDRAM0_PGE

MEGA_PUP_REQ=MEGA_PUP_REQ_0, MEGA_PDN_REQ=MEGA_PDN_REQ_0, PDRAM0_PGE=PDRAM0_PGE_0

Description

GPC Interface control register

Fields

MEGA_PDN_REQ

MEGA domain power down request

0 (MEGA_PDN_REQ_0): No Request

1 (MEGA_PDN_REQ_1): Request power down sequence
MEGA_PUP_REQ

MEGA domain power up request

0 (MEGA_PUP_REQ_0): No Request

1 (MEGA_PUP_REQ_1): Request power up sequence
PDRAM0_PGE

FlexRAM PDRAM0 Power Gate Enable

0 (PDRAM0_PGE_0): FlexRAM PDRAM0 domain will keep power even if the CPU core is powered down.

1 (PDRAM0_PGE_1): FlexRAM PDRAM0 domain will be powered down when the CPU core is powered down…

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data